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3D-printed microdevices have become increasingly important to the advancement of point-of-care (POC) immunoassays. Despite its great potential, using 3D-printed surfaces on the solid support for immunorecognition has been limited due to the non-ideal adsorption properties for many photocurable resins. In this work, we report a simple surface modification protocol that works for diverse commercial photocurable resins, improving ELISAs performed directly on 3D-printed devices. This surface modification strategy involves surface activation via air plasma followed by the one-step incubation of GLYMO-labeled streptavidin. We successfully immobilized biotinylated anti-activin A antibodies on the 3D-printed surfaces and performed the complete ELISA protocol on the 3D-printed surfaces. We demonstrated that this protocol achieved an improved performance over passive adsorption for ELISAs. The present method is also compatible with diverse commercial resins and works with both microwells and microchannels. Finally, this method demonstrated a comparable limit of detection to the ELISA performed using commercial microwells. We believe the simplicity and broad compatibility of the present surface modification strategy will facilitate the development of 3D-printed POC ELISA devices. 

Predicting the minimum operating voltage Vmin of chips stands as a crucial technique in enhancing the speed and reliability of manufacturing testing flow. However, existing Vmin prediction methods often overlook various sources of variations in both training and deployment phases. Notably, overlooking wafer zone-to-zone (intra-wafer) variations and wafer-to-wafer (inter-wafer) variations diminishes the accuracy, data efficiency, and reliability of Vmin predictors. To address this challenge, we propose Restricted Bias Alignment (RBA), a novel data-efficient Vmin prediction framework that introduces a variation alignment technique to simultaneously estimate inter- and intra-wafer variations. Furthermore, we propose utilizing class probe data to model inter-wafer variations for the first time. 

The increasing complexity of electronic systems in autonomous electric vehicles necessitates robust methods for forecasting the degradation of critical components such as printed circuit boards (PCBs). Various time series forecasting methods have been investigated to predict in-situ resistance degradation under vibration loads. However, these methods failed to capture the degradation trend under strong measurement noise. This paper introduces Monotonic Segmented Linear Regression (MSLR), a novel approach designed to capture monotonic degradation trends in time series data under significant measurement noise. By incorporating monotonic constraints, MSLR effectively models the non-decreasing behavior characteristic of degradation processes. To further enhance reliability of the prediction, we integrate Adaptive Conformal Inference (ACI) with MSLR, enabling the estimation of statistically valid upper bounds for resistance degradation with high confidence. Extensive experiments demonstrate that MSLR outperforms state-of-the-art time series forecasting baselines on real-world PCB degradation datasets. 

Analog circuit design requires substantial human expertise and involvement, which is a significant roadblock to design productivity. Bayesian Optimization (BO), a popular machine-learning-based optimization strategy, has been leveraged to automate analog design given its applicability across various circuit topologies and technologies. Traditional BO methods employ black-box Gaussian Process surrogate models and optimized labeled data queries to find optimization solutions by trading off between exploration and exploitation. However, the search for the optimal design solution in BO can be expensive from both a computational and data usage point of view, particularly for high-dimensional optimization problems. This paper presents ADO-LLM, the first work integrating large language models (LLMs) with Bayesian Optimization for analog design optimization. ADO-LLM leverages the LLM’s ability to infuse domain knowledge to rapidly generate viable design points to remedy BO's inefficiency in finding high-value design areas specifically under the limited design space coverage of the BO's probabilistic surrogate model. In the meantime, sampling of design points evaluated in the iterative BO process provides quality demonstrations for the LLM to generate high-quality design points while leveraging infused broad design knowledge. Furthermore, the diversity brought by BO's exploration enriches the contextual understanding of the LLM and allows it to more broadly search in the design space and prevent repetitive and redundant suggestions. We evaluate the proposed framework on two different types of analog circuits and demonstrate notable improvements in design efficiency and effectiveness.